As a conventional printed circuit board, enclosing a capacitor in a substrate thereof, there is disclosed in Patent Document 1 (JP Patent No. 2738590) the configuration of a capacitor laminate which is composed of an organic dielectric layer sandwiched between conductor layers and which may operate as a capacitor. However, with the configuration described in this Patent Document 1, the capacitance cannot be raised beyond a limit value of several nF at most.
In a well-known manner, there are three techniques of increasing the capacitance C of a capacitor, namely    the technique of increasing the surface areas of the electrodes;    the technique of decreasing the spacing between the electrodes (that is, of reducing the thickness of the dielectric layer between the electrodes); and    the technique of increasing the dielectric constant of the dielectric layer.
Turning to the above techniques, it is practically difficult, from the perspective of product reliability, such as electrical insulating properties, and the manufacture process, to set the film thickness of the dielectric layer to 1 μm or less. It is similarly difficult to drastically increase the dielectric constant of the dielectric layer. The Patent Document 1 teaches roughening the metal surface for apparently increasing its surface area. However, with the method disclosed in the Patent Document 1, the surfaces of the electrodes, facing each other, cannot be increased, as a result of which sufficient properties cannot be achieved.
On the other hand, Patent Document 2 (JP Patent Kokai Publication No. JP-P2001-320171A) discloses a configuration comprising a dielectric layer for a capacitor of aluminum oxide, formed for covering up the surface of an aluminum substrate, and a plating layer for a capacitor electrode, formed for covering up the surface of the dielectric layer for the capacitor. The aluminum substrate, dielectric layer for a capacitor and the plating layer for a capacitor electrode make up a capacitor in a multi-layer circuit substrate, whereby the necessity of burying a chip capacitor in an inter-layer insulating film may be removed to render it possible to reduce the film thickness of the inter-layer insulating film and hence the thickness of the multi-layer circuit substrate in its entirety. However, the aluminum oxide film, formed by sintering a powdered material, is not up to coping with the demand for reduction of film thickness.
For solving the above problem, the present inventors have already proposed the configuration of a capacitor enclosed in a printed circuit board making use of a metal core of e.g. aluminum to enable storage of electrical charges of larger capacities (see Patent Document 3). FIG. 6 shows one of the configurations proposed in the above Patent Document 3. Referring to FIG. 6, for preparing this state-of-the-art capacitor, it is necessary to carry out the steps of covering the perimeter of an aluminum oxide layer 12, formed on the surface of the aluminum plate 11, with an electrically conductive high polymer layer 13, selectively forming an electrically conductive paste 15 in a cathode side electrode contact area (via-forming area), and removing the electrically conductive high polymer layer 13 and the aluminum oxide layer 12 on the anode side for exposing the surface of the aluminum plate 11, as shown in FIG. 6.
[Patent Document 1]
JP Patent No. 2738590
[Patent Document 2]
JP Patent Kokai Publication No. JP-P2001-320171A
[Patent Document 3]
JP Patent Kokai Publication No. JP-P2004-31641A